This week on the IEEE Electronic Components and Packaging Technology Conference, Intel unveiled that it’s growing new chip packaging expertise that may enable for larger processors for AI.
With Moore’s Regulation slowing down, makers of superior GPUs and different information middle chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most measurement of a single silicon chip is mounted at round 800 sq. millimeters (with one exception), so that they’ve needed to flip to advanced packaging technologies that combine a number of items of silicon in a means that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC have been aimed toward tackling limitations in simply how a lot silicon you’ll be able to squeeze right into a single package deal and the way large that package deal will be. They embody enhancements to the expertise Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct methodology for bonding silicon to the package deal substrate, and system to increase the dimensions of a important a part of the package deal that take away warmth. Collectively, the applied sciences allow the mixing of greater than 10,000 sq. millimeters of silicon inside a package deal that may be larger than 21,000 mm2—an enormous space concerning the measurement of 4 and a half credit cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single package deal has to do with connecting a lot of silicon dies at their edges. Utilizing an natural polymer package deal substrate to interconnect the silicon dies is probably the most reasonably priced possibility, however a silicon substrate means that you can make extra dense connections at these edges.
Intel’s answer, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural package deal beneath the adjoining edges of the silicon dies. That sliver of silicon, referred to as EMIB, is etched with tremendous interconnects that improve the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the newest twist on the EMIB expertise, referred to as EMIB-T. Along with the same old tremendous horizontal interconnects, EMIB-T supplies comparatively thick vertical copper connections referred to as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board beneath to instantly connect with the chips above as a substitute of getting to route across the EMIB, decreasing energy misplaced by an extended journey. Moreover, EMIB-T incorporates a copper grid that acts as a floor aircraft to cut back noise within the energy delivered attributable to course of cores and different circuits abruptly ramping up their workloads.
“It sounds easy, however it is a expertise that brings a variety of functionality to us,” says Rahul Manepalli, vice chairman of substrate packaging expertise at Intel. With it and the opposite applied sciences Intel described, a buyer might join silicon equal to greater than 12 full measurement silicon dies—10,000 sq. millimeters of silicon—in a single package deal utilizing 38 or extra EMIB-T bridges.
Thermal management
One other expertise Intel reported at ECTC that helps improve the dimensions of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the expertise used as we speak to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they may connect with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the package deal’s interconnects to the silicon’s.
As a result of the silicon and the substrate increase at completely different charges when heated, engineers must restrict the inter-bump distance, or pitch. Moreover, the growth distinction makes it troublesome to reliably make very giant substrates filled with a number of silicon dies, which is the route AI processors must go.
The brand new Intel tech makes the thermal growth mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates will be populated with dies. Alternatively, the identical expertise can be utilized to extend the density of connections to EMIB right down to about one each 25 micrometers.
A flatter warmth spreader
These larger silicon assemblages will generate much more warmth than as we speak’s methods. So it’s important that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of steel referred to as a warmth spreader is vital to that, however making one large enough for these giant packages is troublesome. The package deal substrate can warp and the steel warmth spreader itself may not keep completely flat; so it may not contact the tops of the new dies it’s purported to be sucking the warmth from. Intel’s answer was to assemble the built-in warmth spreader in elements as a substitute of as one piece. This allowed it so as to add further stiffening parts amongst different issues to maintain every thing in flat and in place.
“Holding it flat at larger temperatures is a giant profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nevertheless, they may doubtless must arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s planned packaging expansion.
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